In EEPROM memories, the value of a bit stored in the memory cell is represented by the value of the threshold voltage of a floating-gate transistor which may be modified at will by erasing or programming operations. The programming or erasure of a floating-gate transistor includes the injection or extraction of electrical charges into the gate of the transistor by tunnel effect (Fowler-Nordheim effect) using a programming/erasure high voltage Vpp in the range of 10 to 20 volts.
The reading of a memory cell having a floating-gate transistor includes comparing the threshold voltage Vt of the transistor with a reference voltage Vt0 that is substantially in the middle between the negative threshold voltage of a programmed transistor and the positive threshold voltage of an erased transistor. In practice, this comparison is made by the application, to the transistor gate, of a read voltage Vread that is substantially equal to Vt0 and then by observing whether the transistor is on or off. The on state or off state of the transistor is detected by a read circuit generally called a read amplifier (or “sense amplifier”), connected to the bit line to which the floating-gate transistor is itself connected. During the reading process, an erased transistor remains off because its threshold voltage is higher than Vread. No current flows in the bit line and this corresponds by convention to a bit equal to 0 at output of the read circuit (certain memories use an opposite convention). A programmed transistor on the contrary is On because its threshold voltage is below Vread. A current flows in the bit line and this corresponds by convention to a bit equal to 1 at output of the read circuit.
It is assumed that the threshold voltage Vt of the transistor will remain stable in time, normally for several years, under specified conditions of temperature and use. In other words, the electrical charges injected into the gate of the transistor remain indefinitely trapped therein so long as a reverse erasure operation is not performed, and the extracted electrical charges do not, in principle, return into the erased gate so long as a reverse programming operation is not performed. However, manufacturing defects may sometimes affect the stability of certain cells, occasionally leading to an error in the reading of a bit. For example, the negative threshold voltage of a programmed transistor may develop slowly towards a positive value higher than Vread. There is then data corruption so that a “0” is read in the memory instead of the initially recorded “1”, or vice versa.
For this reason, the secured-type EEPROM memories are provided with an error Correction circuit that generates an error correction code, or [ECC code] ECC, before each recording of a binary word. An [ECC code] ECC of this kind is concatenated with the binary word and recorded in the memory jointly with this word. When the word is then read in the memory, the [ECC code] ECC that accompanies it makes it possible to detect the presence, if any, of an erroneous bit in the word and to correct the bit.
The drawback of a secured memory, is that, for a given storage capacity, it requires a number of memory cells that is appreciably greater than that of a non-secured memory because a portion of the memory cells is reserved for the storage of the [ECC code] ECC bits. To reduce the ratio between the number of veils designed for the storage of the [EEC codes] ECC and the number of cells receiving data bits, it is advantageous to associate an [ECC code] ECC with several binary words rather than to associate one [ECC code] ECC with each binary word. Thus, for example, a Hamming code used to detect and correct a wrong bit in a bit string must include:                at least 4 bits for a string of 8 bits giving a total of 12 bits to be recorded in the memory and a rate of occupation of memory space by code bits equal to about 33%,        at least 5 bits for a string of 16 bits giving a rate of occupation of memory space by code bits of about 24%,        at least 6 bits for a string of 32 bits, giving a rate of occupation of memory space by code bits of about 16%, etc.        
The association of an [ECC code] ECC with a bit string comprising several concatenated binary words is thus an advantageous solution for reducing the number of code bits in a memory. However, the implementing of a method for the concatenation of binary words designed to form strings of very long bits containing an [ECC code] ECC is hardly practical in a page programmable EEPROM memory.
Indeed, in a memory of this kind, the number of programming latches must be identical to the number of bits in a page to enable the simultaneously recording of an entire page. When a specified binary address word has to be recorded within a bit string comprising other binary words and an [ECC code] ECC, it is necessary to read the complete bit string in the memory, insert the binary word therein by crushing the former word with the same address, compute a new [ECC code] ECC and insert the new [ECC code] ECC in overwriting the former [ECC code] ECC. The new bit string comprising the new binary word and the new [ECC code] ECC is then loaded into the programming latches. However, if another word of the same bit string has to be then replaced by a new word before the activation of the programming step, it is no longer possible to access the bit string if it has been loaded into the latches.
To overcame this drawback, a standard approach includes the temporary storage of the bit strings in a read and write accessible buffer register before the loading of the latches. So long as the bit strings are in the buffer register, they can be modified at will with the insertion of a new [ECC code] ECC at each modification. The drawback of this approach lies in the very existence of the buffer register which requires considerable space and makes the memory more complicated and costly to make. Thus, for example, a memory comprising pages of 128 binary words recorded in pairs of words accompanied by an [ECC code] ECC requires a buffer register capable of the storage, before the loading of latches, of the 128 binary words of the page with, in addition, the associated [ECC codes] ECC.